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PFS7329H 参数 Datasheet PDF下载

PFS7329H图片预览
型号: PFS7329H
PDF下载: 下载PDF文件 查看货源
内容描述: 高功率PFC控制器,集成高压MOSFET和二极管Qspeed的 [High Power PFC Controller with Integrated High-Voltage MOSFET and Qspeed Diode]
分类和应用: 二极管功率因数校正高压控制器
文件页数/大小: 30 页 / 4360 K
品牌: POWERINT [ Power Integrations ]
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PFS7323-7329  
which is essential to meet many efficiency directives. The  
degree of frequency slide is also controlled as a function of  
peak input line voltage, at high input line the maximum off-time  
voltage reference at zero error-voltage will be approximately 1/4  
of the maximum value at low input line conditions.  
threshold when the power good signal transitions from the ‘on’  
state to the high-impedance high-state as the PFC output  
voltage falls out of regulation.  
The POWER GOOD THRESHOLD pin has an internal 100 ms  
de-glitch filter (tPG) to prevent noise events from falsely setting  
the VPG(L) threshold.  
The lower VOFF slope reduces the average frequency swing for  
high input line operation.  
In the event a load fault prevents the boost from achieving  
regulation (~95% of the set output voltage threshold) the PG  
function will remain in the high-impedance state and will not  
annunciate when a output voltage has fallen below the user  
programmed VPG(L) threshold.  
Burst-Mode for No-Load Power Consumption Reduction  
Unlike the original HiperPFS which had the ability to reduce the  
minimum on-time to zero, the minimum on-time in HiperPFS-2  
has a minimum value of 500 ns to enable burst-mode operation  
at no-load.  
The VPG(L) user programmed threshold is enabled once VPG(H)  
threshold has been reached.  
Since the minimum on-time is 500 ns, at no-load the output  
voltage will climb until the device shuts off due to the voltage on  
the COMPENSATION pin reaching the COV threshold. The  
output voltage ripple at no-load to light load will be increased as  
a result of the burst-mode operation.  
If the PGT programming resistor is left open, the power good  
function is disabled and remains in the high-impedance (‘off’)  
state, whereas if the POWER GOOD THRESHOLD pin is  
shorted to the GROUND pin the power good signal will remain  
in the low (‘on’) state until the PFC output voltage has fallen to  
the CUV threshold.  
A higher minimum on-time and inclusion of the COV comparator  
are the main elements in the design to enable this burst-mode  
operation at no-load. The burst-mode was added to reduce the  
power stage no-load consumption to below 0.5 W when the  
boost converter is designed with a ferrite boost choke.  
Similar to the condition described above, if the value of the PGT  
resistor is such that the VPG(L) threshold is greater than the VPG(H)  
threshold the PG signal will remain in the high-impedance off-  
state.  
Power Good Signal (PG)  
The HiperPFS-2 features a ‘power good’ (PG) circuit which  
comprises of an internal comparator that at start-up turns ‘on’ a  
switch when the sensed output voltage on the FEEDBACK pin  
rises to ~95% (VPG(H) threshold) of the set output voltage threshold.  
During start-up prior to the output voltage reaching VPG(H) the PG  
signal is in a high-impedance state (internal switch is in ‘off’ state).  
Power good function is not valid under the following conditions:  
A. VCC is not in a valid range. Below VCC-, the power good  
function is not valid.  
B. REFERENCE pin resistor is in an invalid range. If the  
REFERENCE pin resistor is not either 24. 9 kW for ‘Full’ or  
49.9 kW for ‘Efficiency’ mode, the power good signal is not  
valid. Power good will go to high-impedance state (internal  
MOSFET is ‘off’) at the end of the fast soft-shutdown initiated  
by the REFERENCE pin resistor fault.  
C. The valid programming range of PGT is between 275 V to  
360 V. Programming an output voltage below 275 VDC to  
trigger PG is invalid.  
When the AC input voltage is removed or other fault occurs  
after start-up, the power good signal transitions from ‘on’ to ‘off’  
state once the sensed output voltage on the FEEDBACK pin  
falls to a user selected threshold programmed with a resistor on  
the POWER GOOD THRESHOLD pin. The POWER GOOD  
THRESHOLD pin has a fixed source current of IPGT and this  
combined with the power good threshold resistor sets the  
Set internally  
100% VOUT (380 V)  
by VPG(H)  
95% VOUT (361 V)  
Output Voltage  
Rising  
Set externally  
by RPG  
87.5% VOUT (333 V)  
0.875 # VREF  
IPG  
5.25 V  
50 nA  
RPG  
=
=
= 105 kX  
Output Voltage  
Falling  
tPG  
tPG  
PG = High Impedance  
PG = On-State  
PG = High Impedance  
PI-6700-040512  
Figure 11. Power Good Function Description.  
8
Rev. B 06/13  
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