PFS7323-7329
For high performance designs, use of Litz wire is recommended
to reduce copper loss due to skin effect and proximity effect.
For toroidal inductors the numbers of layers should be less than
3 and for bobbin wound inductors, inter layer insulation should
be used to minimize inter layer capacitance. For ferrite core
inductor, a nominal KP value of 0.35 is recommended for an
optimal design. For Sendust core inductor, a nominal KP value
of 0.6 is recommended for an optimal design.
Line-Sense Network
The line-sense network connected to the VOLTAGE MONITOR
pin provides input voltage information to the HiperPFS-2. The
value of this resistance sets the brown-in and brown-out
threshold for the part. A value of 4 MW is recommended for use
with the universal input parts. Only 1% tolerance resistors are
recommended. This resistance value may be modified to adjust
the brown-in threshold if required however change of this value
will affect the maximum power delivered by the part.
Output Capacitor
For a 385 V nominal PFC, use of a electrolytic capacitor with
450 V or higher continuous rating is recommended. The
capacitance required is dependent on the acceptable level of
output ripple and any hold-up time requirements. The equations
below provide an easy way to determine the required capacitance
in order to meet the hold-up time requirement and also to meet
the output ripple requirements. The higher of the two values
would be required to be used.
A decoupling capacitor of 22 nF is required to be connected
from the VOLTAGE MONITOR pin to the GROUND pin of the
HiperPFS-2 for the universal input parts. This capacitor should
be placed directly at the IC on the circuit board.
Feedback Network
A resistor divider network that provides 6 V at the FEEDBACK
pin at the rated output voltage should be used. The compensation
elements are included with the feedback divider network since
the HiperPFS-2 does not have a separate pin for compensation.
The HiperPFS-2 based PFC has two loops in its feedback. It
has an inner current loop and a low bandwidth outer voltage
loop which ensures high input power factor. The compensation
RC circuit included with the feedback network reduces the
response time of the HiperPFS-2 to fast changes in output
voltage resulting from transient loads.
Capacitance required for meeting the hold-up requirement is
calculated using the equation:
#
#
POUT tHOLD_UP
2
2
CO =
VOUT2 - VOUT MIN
^
h
CO
PO
PFC output capacitance in F.
PFC output power in watts.
tHOLD-UP Hold-up time specification for the power supply
in seconds.
The recommended circuit and the associated component
values are shown in Figure 15.
VOUT
Lowest nominal output voltage of the PFC in volts.
VOUT(MIN) Lowest permissible output voltage of the PFC at
the end of hold-up time in volts.
+
B
D
K
Capacitance required for meeting the low frequency ripple
specification is calculated using the equation:
R1
R3
IO MAX
^
h
R2
C1
PG
VCC
FB
CO =
#
#
#
2
r # fL DVL hPFC
CONTROL
fL
Input frequency in Hz.
R6
∆VO
ηPFC
IO(MAX)
Peak-peak output voltage ripple in volts.
PFC operating efficiency.
Maximum output current in amps.
C
HiperPFS-2
PGT
R7
D1
R5
C2
S
V
G
R
CC
R4
Capacitance calculated using the above method should be
appropriately increased to account for ageing and tolerances.
CR
C3
RR
PI-6989-041813
Power Supply for the IC
A 12 V regulated supply should be used for the HiperPFS-2. If
the VCC exceeds 15 V, the HiperPFS-2 may be damaged. In
most applications a simple series pass linear regulator made
using an NPN transistor and Zener diode is adequate since the
HiperPFS-2 only requires approximately 3.4 mA maximum for
its operation.
Figure 15. Recommended Feedback Circuit.
Resistors R1 to R4 comprise of the main output voltage divider
network. The sum of resistors R1, R2 and R3 is the upper
divider resistor and the lower feedback resistor is R4. Capacitor
C1 is a soft-finish capacitor that reduces output voltage
overshoot at start-up. Capacitor CC is to filter any switching
noise from coupling into the COMPENSATION pin. Resistor R7
and capacitor C3 is the loop compensation network which
It is recommended that a 3.3 mF or higher, low ESR ceramic
capacitor be used to decouple the VCC supply. This capacitor
should be placed directly at the IC on the circuit board.
14
Rev. B 06/13
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