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LNK500P-TL 参数 Datasheet PDF下载

LNK500P-TL图片预览
型号: LNK500P-TL
PDF下载: 下载PDF文件 查看货源
内容描述: 高效节能, CV或CV / CC切换为非常低的成本适配器和充电器 [Energy Efficient, CV or CV/CC Switcher for Very Low Cost Adapters and Chargers]
分类和应用:
文件页数/大小: 20 页 / 503 K
品牌: POWERINT [ Power Integrations ]
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LNK500  
Quick Design Checklist  
3. Thermal check At peak output power, minimum input  
voltage and maximum ambient temperature, verify that the  
temperature specifications are not exceeded for LinkSwitch,  
transformer, output diode and output capacitors. Enough  
thermal margin should be allowed for part-to-part variation  
of the RDS(ON) of LinkSwitch as specified in the data sheet.  
Under low line, peak power, a maximum LinkSwitch  
SOURCE pin temperature of 100 °C is recommended to  
allow for these variations.  
Aswithanypowersupplydesign,allLinkSwitchdesignsshould  
be verified on the bench to make sure that component  
specifications are not exceeded under worst case conditions.  
Note:Ina LinkSwitch circuit, theSOURCEisaswitchingnode.  
This should be taken into consideration during testing.  
Oscilloscope measurements should be made with probe  
grounded to DC voltages such as primary return or DC rail but  
not to SOURCE. Power supply input voltage should always be  
suppliedusinganisolationtransformer. Thefollowingminimum  
set of tests is strongly recommended:  
4. Centered output characteristic Using a transformer with  
nominal primary inductance and at an input voltage midway  
between low and high line, verify that the peak power point  
occursatthedesirednominaloutputcurrent, withthecorrect  
output voltage. If this does not occur then the design should  
be refined to ensure the overall tolerance limits are met.  
1. Maximum drain voltage Verify that VDS does not exceed  
675 V at highest input voltage and peak output power.  
2. MaximumdraincurrentAtmaximumambienttemperature,  
maximum input voltage and peak output power, verify drain  
current waveforms at start-up for any signs of transformer  
saturation and excessive leading edge current spikes.  
LinkSwitch has a minimum leading edge blanking time of  
200 ns to prevent premature termination of the on-cycle.  
Verify that the leading edge current spike event is below  
current limit at the end of the 200 ns blanking period.  
Design Tools  
Up to date information on design tools can be found at the  
Power Integrations Web site: www.powerint.com.  
Input Filter  
Capacitor  
D
S
C
+
LinkSwitch  
HV DC  
Input  
-
S
S
S
S
Transformer  
Y1-  
Capacitor  
-
DC Out  
+
Output  
Capacitor  
PI-2900-070202  
Figure 11. Recommended Circuit Board Layout for LinkSwitch using P Package.  
B
3/03  
10