LCS700-708
Bursting Duty ≈ 50%
10 μs / div
3.4 V
VREF
CSTART
RFMIN
RSTART
U1B
IPRI
VHB
850 ns / div
D1
FB
ROPTO
CFB
4.7 nF
RLOAD
GND
~850 kHz
Severe Loss of ZVS
PI-6118-051711
Figure 20. Bursting at fMAX Causes High Internal Dissipation Due to Loss of
ZVS and Should be Avoided.
Figure 19. Feedback Network Shown with Additional Load Resistor.
300
start-up frequency, and fSTART, which is the burst mode start
(lower) threshold frequency.
100
50
The FEEDBACK pin current at start-up is determined by the value
of RSTART because the voltage on CSTART will be zero. For minimum
start-up peak currents, this current should match or slightly
exceed the DT/BF pin current so that start-up switching frequency
begins at fMAX. The resulting value of RSTART will be approximately
10% lower than the value of the pull-up resistor on the DT/BF pin.
The frequency will slide down as CSTART charges. If RSTART is
smaller than that which provides start-up at fMAX, it will create an
additional delay before start-up switching. Please see the PIXls
HiperLCS spreadsheet.
20
10
4
20
50
100
200
500
1000
Frequency (kHz)
Resistor RLOAD provides a load on the optocoupler, and speeds
up the large signal transient response during burst mode. The
recommended value is ~4.7 kW. Diode D1 prevents RLOAD from
loading RFMIN when the optocoupler is cut off. Diode D1 can be
omitted and a combination of resistor values found to achieve the
desired fMIN but the resulting tolerances will be poor. Resistor
ROPTO will improve the ESD and surge immunity of the PSU. It
also improves burst mode output ripple voltage. Its maximum
value must be such that the FEEDBACK pin current is equal to
the DT/BF pin current when the optocoupler is in saturation and
the FEEDBACK pin is at 2.0 V (please see PIXls HiperLCS
spreadsheet). This is to ensure that if the HiperLCS does not exit
start-up mode, because the feedback loop did not allow the
switching frequency to drop below fSTOP, then it can regulate at
light load by bursting at fMAX. Note however bursting at fMAX can
lead to high internal dissipation due to loss of ZVS and should be
avoided. See Figure 20.
Figure 21. VREF to FB External Resistance vs. Frequency.
In order to calculate RFMIN and RSTART, use the following equation
which describes nominal resistance from FEEDBACK pin to
VREF pin, vs. frequency:
3574
^0.6041+0.1193#LOG^ fhh
RFB
=
f
Where RFB is in kW and f is in kHz.
To calculate the minimum RSTART, which produces start-up at fMAX
use the above equation with f = fMAX from the equation relating
,
dead-time and fMAX
.
To set fMIN, use the above equation with f = fMIN × 0.93. Where
0.93 is to ensure that, despite the worst case frequency tolerance
of -7%, the frequency can go below fMIN, guaranteeing regulation
at VBROWNOUT
.
Capacitor CSTART should be sized at the minimum possible value
that exhibits a 7 consecutive-cycle peak current at start-up that is
just below the peak current measured at brown-out and full load.
A larger value will slow down start-up and will make it more likely
that fSTOP is not reached. This can prevent exiting start-up mode
when the HiperLCS is powered up at high-line and minimum load,
and may subsequently cause the HiperLCS to burst at fMAX
Using the resulting calculated value for RFB, calculate RFMIN
:
R
FMIN = RFB - RSTART
The sum of RFMIN and RSTART determines fMIN
.
instead of between fSTART and fSTOP
.
15
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Rev. B 062011
POWERINT [ Power Integrations ]
