ZM7300G Series Digital Power Manager
Data Sheet
8.4
I2C Interface
Parameter
Conditions/Description
Input low voltage
Min
-0.5
Nom
Max
Units
V
ViL
ViH
Vhys
VoL
tr
0.3·VDD
VDD+0.5
Input high voltage
0.7·VDD
0.05·VDD
0
V
Input hysteresis
V
Output low voltage, ISINK=3mA
Rise time for SDA and SCL
Output fall time from ViHmin to ViLmax
Input current each I/O pin, 0.1VDD<Vi<0.9VDD
Capacitance for each I/O pin
SCL clock frequency
0.4
300
250
10
V
1
20+0.1Cb
20+0.1Cb
-10
ns
ns
μA
pF
kHz
1
tof
Ii
Ci
10
fSCL
0
400
Standard-Mode I2C (fSCL ≤ 100kHz)
1
RPU
tHDSTA
tLOW
External pull-up resistor
Hold time (repeated) START condition
Low period of the SCL clock
1
1000/Cb
kΩ
μs
μs
μs
μs
μs
ns
μs
μs
4.0
4.7
4.0
4.7
0
tHIGH
High period of the SCL clock
tSUSTA
tHDDAT
tSUDAT
tSUSTD
tSUF
Setup time for a repeated START condition
Data hold time
3.45
Data setup time
250
4.0
4.7
Setup time for STOP condition
Bus free time between a STOP and START condition
Fast-Mode I2C (100kHz < fSCL≤ 400kHz)
1
RPU
tHDSTA
tLOW
External pull-up resistor
Hold time (repeated) START condition
Low period of the SCL clock
1
300/Cb
kΩ
μs
μs
μs
μs
μs
ns
μs
μs
0.6
1.3
0.6
0.6
0
tHIGH
High period of the SCL clock
tSUSTA
tHDDAT
tSUDAT
tSUSTD
tSUF
Setup time for a repeated START condition
Data hold time
0.9
Data setup time
100
0.6
1.3
Setup time for STOP condition
Bus free time between a STOP and START condition
______________________________________
1
Cb – bus capacitance in pF, typically from 10pF to 400pF
to
f
tHIG
H
tLO
W
tr
tLO
W
SCL
SDA
tSUST
A
tHDST
A
tHDDA tSUDA
tSUST
O
T
T
tBU
F
Figure 2. I2C Timing Parameters
www.power-one.com
ZD-00896 Rev. 5.1, 13-Jul-10
Page 6 of 33
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