ZM7300G Series Digital Power Manager
Data Sheet
12
Pins Description
ACFAIL_N, AC Fail Input (Pin 16): Schmitt-Trigger
input with internal pull-up resistor (active low).
Pulling low the input indicates to the DPM that an
AC-DC front-end has lost the mains and that a
system shut down should immediately be initiated.
released, POLs are assumed to be disconnected
from the DPM.
IR, Internal Reset (Pin 63): Connect to VSS via a
10kOhm resistor.
ADDR[0:2], I2C Address Inputs (Pins 47, 46, 45):
Inputs with internal pull-up resistor. The 3 bit
LCK_N, Memory Lock (Pin 61): Active low input
with internal pull-up. When LCK_N is pulled low, all
memory within the DPM is write-protected. The write
protection cannot be disabled by software.
encoded
address
determines
the
DPM
communication address for the I2C interface.
AREF, Analog Reference (Pin 44): An analog
reference which is used internally. A 10nF capacitor
should be connected as close as possible to the
package between AREF and VSS. See 10.4.4.1.
OKA, OKB, OKC, OKD, Group OK Signals (Pins
11, 13, 20, 53): An open drain input/output with
internal pull-up resistor. Pulling low the OK input will
indicate to the DPM a fault in a Group, the DPM can
also pull an OK line low to disable a Group.
CB, Crowbar Output (Pin 23): A CMOS output
which is used to trigger a crowbar (SCR) in case of
overvoltage on the Intermediate Voltage Bus.
PG[0:3], Power Good (Pins 54, 52, 51, 49): Input
with internal pull-up resistor. The pin is used to read
the status of an Auxiliary Device.
EN[0:3], Enable Outputs for Auxiliary Devices
(Pins 5, 7, 55, 50): CMOS outputs to control
Auxiliary Devices like linear regulators, analog POLs,
fans or other devices.
RES_N, Active Low Reset In/Out (Pin 18): Input
with internal pull-up resistor. When pulled low a soft
reset of the system (sequenced turned off of all
POLs and Auxiliary Devices) is initiated. When
released the whole system is reprogrammed and
started if necessary.
.
FE_EN, Front-End Enable (Pin 17): A CMOS
output which is used to turn-on/off the DC/DC
converter generating the IBV.
SD, Sync Data Line (Pin 56): An open drain input /
output with internal pull-up resistor. Communication
line to distribute a master clock to all converters and
at the same time to communicate with all POLs.
HRES_N, Hardware Reset (Pin 4): Input with
internal pull-up resistor. When pulled low a cold start
of the Digital Power Manager is initiated. Refer to
paragraph 10.6.4 for important information regarding
connections of this pin.
JTAG Interface (Pins 34, 33, 32, 31): Connect to a
JTAG
IEEE-1149.1-compliant
programmer
IBVS, Intermediate Voltage Bus Sense (Pin 48):
Analog input to an internal ADC circuit to measure
the Intermediate Bus Voltage. The full scale range
of the input is 2.56V and the IBV should be scaled
down by a factor of 5.7 for proper reporting of the
IBV with the Z-ONE™ GUI.
supporting SVF files or leave open, if not used.
VDD, Positive Supply (Pins 6, 25, 42, 57, 60):
Supply voltage.
At least 4x100nF decoupling
capacitors should be connected between VDD and
VSS pins. All VDD pins must be connected.
INT[0:3], Interrupts (Pins 41, 40, 37, 36): Four
active low inputs with internal pull-ups. Each of the
inputs can be configured for two functions: first, the
interrupt input acts on the OK line(s) to stop
momentarily the operation of group of POLs and
Auxiliary Devices, second the interrupt can be used
as a hot swap trigger. In this function the interrupt
input triggers the programming of a group. When
VSS, Ground (Pins 8, 9, 26, 38, 43, 58): Ground.
Decoupling capacitors need to be connected as
close as possible to the pins. All VSS pins must be
connected.
nc, No Connect (Pin 1, 2, 3, 10, 12, 14, 15, 19, 21,
22, 24, 28, 29, 35, 39, 59, 62, 64): All nc pins must
remain floating.
ZD-00896 Rev. 5.1, 13-Jul-10
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