FNP1500/1800 Front-Ends
& FNR-3 Power Shelf Data Sheet
Output Connector Pinning and Signal Specification
Output Connector
Description
Pin
Location
Type
Low level
High level
V max
I max
Overtemperature /
Fan Fail
< 0.4 V @ 20 mA
Pull up
15 V
20 mA
OC-output, protected by 16 V Zener diode and a 10 Ω
U1
U2
U3
U4
resistor in series, referenced to logic GND
AC Fail /
Power down warning
OC-output, protected by 16 V Zener diode and a 10 Ω
< 0.4 V @ 20 mA
Pull up
15 V
20 mA
resistor in series, referenced to logic GND
Open
Pull up
10 V
10 mA
Power Supply Present
Resistor (1 kꢀ) connected to logic GND
DC Fail /
Output voltage fault
OC-output, protected by 16 V Zener diode and a 10 ꢀ
< 0.4 V @ 20 mA
Pull up
15 V
20 mA
resistor in series, referenced to logic GND
Internal ground (Vo1– line before the output filter).
Do not connect the internal grounds in
systems with several units.
Internal ground
U5
ADDR0, I2C address
bus
ADDR1, I2C address
bus
ADDR2, I2C address
bus
ADDR3, I2C address
bus
DIP switch or wire to internal ground,
Switch closed
Switch open
5V
5V
5V
5V
5V
T1
T2
T3
T4
Internally pull up to 5V (10 kꢀ).
DIP switch or wire to internal ground,
Switch closed
Switch open
Internally pull up to 5V (10 kꢀ).
DIP switch or wire to internal ground,
Switch closed
Switch open
Internally pull up to 5V (10 kꢀ).
DIP switch or wire to internal ground,
Switch closed
Switch open
Internally pull up to 5V (10 kꢀ).
ADDR4, I2C address
bus
DIP switch or wire to internal ground,
Switch closed
Switch open
T5
Internally pull up to 5V (10 kꢀ).
I2C compatible signal
referenced to logic GND
I2C compatible signal
DATA, I2C data line
S1
S2
5 V or 3.3 V logic
5 V or 3.3 V logic
CLOCK, I2C clock line
referenced to logic GND
Vo2 + output
Vo2 – output
S3
S4
Auxiliary power pin, insulated from main output
Auxiliary ground pin, insulated from main output
Internally connected over 10 ꢀ to Auxiliary GND. Wire
separately form Auxiliary - and main output GND to
minimize noise on signals and I2C.
Logic ground
S5
Leave open if not used.
PS active when pulled low (DC-DC stage off when left
open) Referenced to logic GND
< 0.8 V
> 2.0 V
10 V
3.5 mA
Output inhibit
V sense +
V sense -
R1
R2
R3
Open or connected to Vo1+ at the load
(Internally connected to Vo1+ over 100 ꢀ)
dU < 3 Vpp
30 mA
Open or connected to Vo1- at the load
(Internally connected to Vo1- over 100 ꢀ)
dU < 3 Vpp
30 mA
Open or connected over resistor to internal ground.
Do not connect the margin pins in
3 VDC
12V models
Output margin
48V models
R4
R4
systems with several units.
Open or connected to internal ground
60 VDC
(+8 % Vo1) or V sense+ (-8 % Vo1)
Do not connect the margin pins in
systems with several units.
12V
3mA
Open or connected to synch startup circuit,
referenced to Vo1 - at the output connector
12V models
Synch. startup
48V models
R5
R5
12V
2mA
Open or connected to synch startup circuit,
referenced to Vo1 - at the output connector
Vo1 + output
12V models
P2, P4, P6, P8,
P10, P12
Main output + pins
Main output – pins
Vo1 – output
12V models
P1, P3, P5,
P7, P9, P11
Vo1 + output
48V models
P2, P4, P6
P1, P3, P5
Main output + pins
Main output – pins
Vo1 – output
48V models
MCD10074 Rev. 1.2, 15-Apr-10
Page 7 of 17
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