8.3
Signal Specifications
Parameter
SDpu
SDthrL
SDthrH
SDhys
SDsink
Freq_sd
Tsynq
T0
Conditions/Description
SYNC/DATA Line
SD pull up resistor
SD input low voltage threshold
SD input high voltage threshold
SD input hysteresis
SD sink capability (V
SD
=0.5V)
Clock frequency
Sync pulse duration
Data=0 pulse duration
5
0.31·VDD
0.45·VDD
0.37
450
22
72
0.52·VDD
0.81·VDD
1.1
30
550
28
78
k
V
V
V
mA
kHz
% of clock
cycle
% of clock
cycle
k
V
V
V
k
V
V
Min
Nom
Max
Units
Interrupt Inputs (INT_N[3:0])
Rpu3
VthrL3
VthrH3
Vhys3
Rpu1
VthrL1
VthrH1
Pull up resistor
Input low voltage threshold
Input high voltage threshold
Input hysteresis
Pull up resistor
Input low voltage
Input high voltage
30
0.31·VDD
0.45·VDD
0.37
20
-0.5
0.7·VDD
0.52·VDD
0.81·VDD
1.1
50
0.2·VDD
VDD+0.5
ADDR[3:0], ACFAIL_N, RES_N, LCK_N, PG[3:0] Inputs
Rpu2
VthrL2
VthrH2
OKpu
OKthrL
OKthrH
OKhys
OKsink
V
EN
V
EN
V
EN
H
V
EN
L
HRES_N Input
HRES_N pull up resistor (with series
30
diode, see note 1)
HRES_N input low voltage
-0.5
HRES_N input high voltage
0.9·VDD
Inputs/Outputs (OK_A, OK_B, OK_C, OK_D)
OK pull up resistor
OK input low voltage threshold
OK input high voltage threshold
OK input hysteresis
OK sink capability (V
OK
=0.5V)
EN logic level enabled
EN logic level disabled
EN output high voltage
I
OH
= -10 mA
EN output low voltage
I
OL
= 5 mA
5
0.31·VDD
0.45·VDD
0.37
60
0.2·VDD
VDD+0.5
k
V
V
k
V
V
V
mA
0.52·VDD
0.81·VDD
1.1
30
High
Low
Enable Outputs (EN[3:0])
VDD-0.6
0.5
V
V
______________________________________
1
HRES_N
Input - Because the input does not have an internal ESD protection diode connected to VDD, the user needs to add an external diode between the
HRES_N and VDD pins as shown in Figure 3.
ZD-00896 Rev. 5.2, 9-Apr-13
www.power-one.com
Page 6 of 36
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