RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Figure 75. Setup and Hold for 3.3V-tolerant 2.5V CMOS and 2.5V CMOS (Serdes Interface)
Reference Clock
tval3
tsus3
Output
tsu3
th3
Input
Figure 76. Rise and Fall Times for 3.3V-tolerant 2.5V CMOS and 2.5V CMOS (Serdes Interface)
tper3
50%
tph3
tpl3
80%
20%
tf3
tr3
Figure 77. Serdes Test Loading
R1=50 Ohm
Test Point
Output
C1=1pF
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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