RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Figure 72. Setup and Hold for 3.3V-tolerant 2.5V CMOS and 2.5V CMOS (JTAG Interface)
Reference Clock
tval2
tsus2
Output
tsu2
th2
Input
Figure 73. Rise and Fall Times for 3.3V-tolerant 2.5V CMOS and 2.5V CMOS (JTAG Interface)
tper2
50%
tph2
tpl2
80%
20%
tr2
tf2
Figure 74. JTAG Test Loading
R1=50 Ohm
Test Point
Output
C1=1pF
310
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE