RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Table 37. Scheduler Signal Descriptions (Continued)
Name
oob_valid_L
I/O
Type
Description
I
CMOS
CMOS
OOB Control
OOB Control
oob_wait_L
O
AIB Interface
p2s_p[31:0]_[c, cn, e,
en, o, on]
I
STI
STI
Port Processor to Scheduler AIB
Scheduler to Port Processor AIB
s2p_p[31:0]_[c, cn, e,
en, o, on]
O
Power Supply, Clock Source, Reset, And Diagnostics
plllock
O
I
CMOS
CMOS
CMOS
Indicates if the PLL has locked (1)
Synchronous, Active Low Reset
Buffered soc_in (NC)
pwrup_reset_in_L
soc_out
O
Isolated
Supply
VDDA
VDD (2.5 V) for PLL
VDD
Supply
Supply
PECL
PECL
VDD (2.5 V)
GND
GND (0 V)
ref_clk and ref_clkn
soc_in and soc_inn
I
I
System 200MHz clock (differential)
System Start-of-cell (differential)
JTAG Interface
CMOS_
2.5_only
jtag_tck
jtag_tdi
I
I
1149.1 JTAG 2.5V ONLY!
CMOS_
2.5_only
1149.1 JTAG 2.5V ONLY!
1149.1 JTAG 2.5V ONLY!
1149.1 JTAG 2.5V ONLY!
1149.1 JTAG 2.5V ONLY!
CMOS_
2.5_only
jtag_tdo
jtag_tms
jtag_trst_L
O
I
CMOS_
2.5_only
CMOS_
2.5_only
I
ASIC Manufacturing Test Interface
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
277
PMC [ PMC-SIERRA, INC ]
