RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
5.4.3 Input Queue Memory (IQM)
The Scheduler has internal memory which stores the number of waiting cells at every input port. This
memory can be read by the CPU. Caution: while the memory can also be modified, doing so may result in
cell loss. CPU access to this memory is provided for diagnostic purposes only. After reset the memory is
cleared to zero.
Each Scheduler port (0:31) has four IQM units, one for each best-effort priority. Each IQM is organized as
two independent memories: the first is 64 words of 32 bits and stores multicast fanout information. The
second is 32 words of 7 bits and stores the number of waiting cells at each unicast virtual output queue.
The individual entries in each IQM are addressed by the CPU as shown below:
3
19
0
15
11
Pri
7
0
M/U
Port
Addr/QID
0
1
0
0
0
Port is the port number 0:31.
Pri is the selected best effort priority 0:3.
M/U is 1 for the multicast fanout memory and 0 for the unicast request count memory.
Addr/QID is the multicast fanout address or a unicast VOQ identifier (only 0:31).
So, for example, unicast VOQ 10 contains the number of requests (cells) that are waiting to go from this
port to output port 10.
The multicast fanout addresses are organized as a circular list. However the head of the list cannot be
determined by the CPU except immediately after a refresh operation, at which time the second entry in the
multicast fanout queue is at location zero. The first entry is held in a private register and is not visible to the
CPU.
Although the IQM should not be modified during normal operation, it is prudent to verify the integrity of the
memory after the Scheduler is reset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
275
PMC [ PMC-SIERRA, INC ]
