Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Table 22. Dataslice Signal Descriptions (Continued)
Name
I/O
Type
Description
xcvr1_com_det
xcvr1_loopback
xcvr1_sig_det
I
O
I
CMOS
CMOS
CMOS
VCSEL and Serdes status signals
VCSEL and Serdes control signals
VCSEL and Serdes status signals
Power Supply, Clock Source, Reset, and Diagnostics
fotx_clk_in
plllock
I
O
I
CMOS
CMOS
CMOS
Clock input used for fotx_clk_out
Test output
pwrup_reset_L
Synchronous, Active Low Reset
Isolated
Supply
VDDA
VDD (2.5 V) for PLL
VDD
Supply
Supply
Supply
PECL
VDD (2.5 V)
VDDQ
VDDQ (1.6 V)
GND
GND (0 V)
ref_clk and ref_clkn
soc_in and soc_inn
I
I
System 200MHz clock (differential)
System Start-of-cell (differential)
PECL
JTAG Interface
CMOS_
2.5_only
jtag_tck
jtag_tdi
I
I
1149.1 JTAG 2.5V ONLY!
1149.1 JTAG 2.5V ONLY!
1149.1 JTAG 2.5V ONLY!
1149.1 JTAG 2.5V ONLY!
1149.1 JTAG 2.5V ONLY!
CMOS_
2.5_only
CMOS_
2.5_only
jtag_tdo
jtag_tms
jtag_trst_L
O
I
CMOS_
2.5_only
CMOS_
2.5_only
I
Dataslice Configuration
crdcrcen0
crdcrcen1
I
I
CMOS
CMOS
DS0 credit CRC enable tied low on all DS devices
DS1 credit CRC enable tied high on physical DS
device 0 only
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
139
PMC [ PMC-SIERRA, INC ]
