Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
2.3.2.23 Input Queue Memory (IQM)
Symbol: DIQM
Address Offset: 40000-5FFFCh
Default Value: Unknown
Access:
Read/Write
The actual IQM address range extends from 40000h to 50FFCh. Beyond IQM address 50FFCh, aliasing
occurs within the IQM 512x48 RAM bank.
If the IQM is accessed at an even 32-bit aligned word address, the data bitmap consists of the following:
Bits
Description
31:16 Reserved.
15:0 This field contains the 16 MSBs of the addressed IQM 48-bit word.
If the IQM is accessed at an odd 32-bit aligned word address, the data bitmap consists of the following:
Bits
Description
31:0
This field contains the 32 LSBs of the addressed IQM 48-bit word
2.3.2.24 Output Queue Memory (OQM)
Symbol: DOQM
Address Offset: 60000- 7FFFCh
Default Value: Unknown
Access:
Read/Write
The actual OQM address range extends from 60000h to 70FFCh. Beyond IQM address 70FFCh, aliasing
occurs within the OQM 512x48 RAM bank.
If the OQM is accessed at an even 32-bit aligned word address, the data bitmap consists of the following:
Bits
Description
31:16 Reserved.
15:0
This field contains the 16 MSBs of the addressed OQM 48-bit word.
If the IQM is accessed at an odd 32-bit aligned word address, the data bitmap consists of the following:
Bits
Description
31:0
This field contains the 32 LSBs of the addressed OQM 48-bit word
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
133
PMC [ PMC-SIERRA, INC ]
