Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
current primary Scheduler then it will automatically consider the other Scheduler as the new primary
Scheduler.
If Scheduler 0 (primary Scheduler) receives a CRC error on information from Enhanced Port Processor 1,
then Scheduler 0 and Scheduler 1 might differ in their state information. In this situation Scheduler 0
immediately disables its AIB links to Enhanced Port Processor 1 and Enhanced Port Processor 2 (and all
Enhanced Port Processors). The Enhanced Port Processors immediately detect the loss of connection to
Scheduler 0 and automatically select Scheduler 1 (secondary Scheduler) to be their new primary
Scheduler. Without CPU intervention, the system has disabled the primary Scheduler, and switched the
Enhanced Port Processors to use the secondary Scheduler. The CPU is informed of this error, and must
undertake the process to refresh the Schedulers.The EPP’s may register Scheduler mismatch interrupts
until the Schedulers are refreshed. The AIB links to other EPPs are not affected.
If Scheduler 1 (secondary Scheduler) receives a CRC error on information from Enhanced Port Processor
1, then Scheduler 1 immediately disables its AIB links to Enhanced Port Processor 1. The Enhanced Port
Processors do not alter their primary/secondary setting, since Scheduler 0 is already selected as the
primary Scheduler. The CPU is notified of this error, and must go through the steps to refresh the
Schedulers.
The actions the Scheduler performs upon detecting a CRC error are different in the redundant and
non-redundant configurations. Consequently the Scheduler must be configured to be in redundant or
non-redundant mode. This configuration is accomplished via the CRC Action bit in the Scheduler’s control
register (SCTRLRS). The CRC Action bit should only be set to 1 for the primary Scheduler in a redundant
configuration.
1.9.3 Flow Control Refresh Procedure
The previous section refers to the process of refreshing flow control state. The purpose of this procedure is
to insure consistency of the state information between the iEPPs and the oEPPs. In the non-redundant
Flow Control Crossbar configuration, the refresh procedure ensures that iEPPs will have correct queue
depth information about oEPPs
The refresh procedure is as follows:
1. Detect invalid incremental credit interrupt on port i. Read invalid incremental credit interrupt
register on port i. The value specifies to which output port j flow could have missing output queue
credits.
2. Write freeze unicast Output Scheduler flows register on port j with a value of 1 << i. This will cause
the Output Scheduler on port j to stop sending cells from port i.
3. Disable the non TDM enable for port i in the Scheduler.
4. Freeze the Scheduler Request Modulator on port i.
5. Read the output unicast queue information memory (queue length) on port j for queues
corresponding to input port i. If port j is in OC-192c mode, then 4 queue lengths are stored. If port j
is in OC-48c mode, then 16 queue lengths are stored.
6. Read the waiting scheduler request count memory on port i for queues corresponding to output
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
97
PMC [ PMC-SIERRA, INC ]
