Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
1.2.9 System Configuration Options
Most of the previous sections have assumed a particular switch configuration consisting of 32 ports of
OC-192c, with 64 byte payload cells and full redundancy. The ETT1 Chip Set has four aspects that can be
configured according to the user’s requirements. Two of these aspects have been described: quad OC48c
versus single OC-192c port, and a redundant system versus a non-redundant system. The other two
aspects are described in this section.
NOTE: All four aspects are orthogonal and so the choice of any one particular aspect does not
limit the choices for the other three aspects.
1.2.9.1 Payload: 64 bytes or 76 bytes
The ETT1 core and LCS protocol are designed to forward fixed length cells. Each LCS cell consists of an
LCS header (8 bytes) and a payload. The size of this payload can be either 64 bytes or 76 bytes. The
choice of payload size is a function of the linecard traffic: 53-byte ATM cells can probably use a 64 byte
payload; fragmented IP packets might obtain greater efficiency with a 76 byte payload.
This flexibility in cell size is due to the way the ETT1 Chip Set slices the cells. Figure 8 shows how an LCS
cell is sliced across the Dataslices and Crossbars.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
