RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
5.5 SCHEDULER SIGNAL DESCRIPTIONS
This section describes the Scheduler signals.
The following notation is used to describe the signal type:
I
Input pin
O
B
Output pin
Bidirectional Input/Output pin
The signal description also includes the type of buffer used for the particular signal:
PECL
STI
PECL are Pseudo-ECL (positive voltage ECL) compatible signals.
STI is a very high-speed asynchronous communications protocol used to connect devices
that may be 1 to 15 meters apart.
HSTL
All HSTL specifications are consistent with EIA/JEDEC Standard, EIA/JESD8-6 “High
Speed Transceivers Logic (HSTL): A 1.5V Output Buffer Supply Voltage based Interface
Standard for Digital Integrated Circuits”, dated 8/95. Refer to these specifications for more
information.
CMOS
The CMOS Buffers are either 3.3 V compatible or 2.5 V Low Voltage TTL compatible
signals, as noted.
Table 37. Scheduler Signal Descriptions
Name
I/O
Type
Description
OOB Interface
oob_ad[7:0]
B
I
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
OOB Address bus
OOB CLock
oob_clk
oob_devsel0
oob_devsel1
oob_devsel2
oob_devsel3
oob_int_hi
oob_int_lo
I
OOB device select
OOB device select
OOB device select
OOB device select
OOB Interrupt
I
I
I
O
O
OOB Interrupt
276
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
