Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
1.1.4 The OOB (Out-Of-Band) Bus
The ETT1 Chip Set requires a local CPU to perform initialization and configuration after the Chip Set is
reset or if the core configuration is changed - perhaps new ports are added or removed, for example. The
OOB bus provides a simple mechanism whereby a local CPU can configure each device.
Logically, the OOB bus provides a 32 bit address/data bus with read/write, valid and ready signals. The
purpose of the OOB bus is for maintenance and diagnostics; the CPU is not involved in any per-cell
operations.
1.2 ARCHITECTURE AND FEATURES
1.2.1 ETT1 Switch Core
An ETT1 switch core consists of four types of entities: Port, Crossbar, Scheduler, and CPU/Clock. There
may be one or more instances of each entity within a switch. For example, each entity might be
implemented as a separate PCB, with each PCB interconnected via a single midplane PCB. Figure 2
illustrates the logical relationship between these entities.
Figure 2. ETT1 Switch Core Logical Interconnects
Crossbar
Linecard
Linecard
Port
Port
Flow Control
Crossbar
Scheduler
CPU/clock
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
