Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
The second interface is between the ETT1 devices and the local CPU. The ETT1 Chip Set requires a local
CPU for configuration, diagnostics and maintenance purposes. A single CPU can control a complete ETT1
core via a common Out-Of-Band (OOB) bus. All of the ETT1 devices have an interface to the OOB bus.
The OOB bus is described in Section 1.1.4 “The OOB (Out-Of-Band) Bus” on page 18.
1.1.3 The LCS Protocol
The Linecard-to-Switch (LCSTM) protocol provides a simple, clearly defined interface between the linecard
and the core. In this section we introduce LCS. There are two aspects to LCS:
•
•
a per-queue, credit-based flow control protocol
a physical interface
The LCS protocol provides per-queue, credit-based flow control from the ETT1 core to the linecard, which
ensures that queues are not overrun. The ETT1 core has shallow (64 cells) queues in both the ingress and
egress directions. These queues compensate for the latency between the linecard and the core. One way
to think of these queues is simply as extensions of the queues within the linecards. The queues
themselves are described further in Section 1.3 “Prioritized Best-Effort Queue Model” on page 30.
The LCS protocol is asymmetrical; it uses different flow control mechanisms for the ingress and egress
flows. For the ingress flow LCS uses credits to manage the flow of cells between the linecards and the
ETT1 core. The core provides the linecard with a certain number of credits for each ingress queue in the
core. These credits correspond to the number of cell requests that the linecard can send to the core. For
each cell request that is forwarded to a given queue in the core the linecard must decrement the number of
credits for that queue. The core sends a grant (which is also a new credit) to the linecard whenever the
core is ready to accept a cell in response to the cell request. At some later time, which is dependent on the
complete traffic load, the cell will be forwarded through the ETT1 core to the egress port. In the egress
direction a linecard can send hole requests, requesting that the ETT1 core does not forward a cell for one
celltime. The linecard can issue a hole request for each of the four best effort unicast or multicast priorities.
If the linecard continually issued hole requests at all four priorities then the ETT1 core would not forward
any best effort traffic to the linecard.
The LCS protocol information is contained within an eight byte header that is added to every cell.
The physical interface that has been implemented in the ETT1 Chip Set is based on a faster version of the
Gigabit Ethernet Serdes interface, enabling the use of off-the-shelf parts for the physical link. This interface
provides a
1.5 Gbit/s serial link that uses 8b/10b encoded data. Twelve of these links are combined to provide a single
LCS link operating at 18 Gbaud, providing an effective data bandwidth that is in excess of an OC-192c link.
NOTE: The LCS protocol is defined in the “LCS Protocol Specification -- Protocol Version 2”,
available from PMC-Sierra, Inc. This version of LCS supersedes LCS Version 1. Version 2
is first supported in the TT1 Chip Set with the Enhanced Port Processor device (also
referred to as the ETT1 Chip Set) and will be supported in future PMC-Sierra products.
The ETT1 implementation of the LCS protocol is described further in Section 1.6 “ETT1
Usage of the LCS Protocol” on page 64.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
17
PMC [ PMC-SIERRA, INC ]
