NSE-8G™ Standard Product Data Sheet
Preliminary
Register 04DH: DCB Interrupt status Register.
Bit
Type
X
I
I
Function
Unused
SWAPI
UPDATEI
FRAMEI
Default
0
X
X
X
Bit 31-3
Bit 2
Bit 1
Bit 0
I
Writing to this register initiates copying of the active connection memory page to the offline
connection memory page. When a page swap is pending (SWAPV =’1’) writing to this register
may cause a corruption of the connection memory pages.
SWAPI
This bit reports and acknowledges a change of state in the SWAPV bit of the Configuration
register. This bit is cleared when this register is read. When enabled by SWAPE, the INT
output reflects the state of this bit.
UPDATEI
The offline page copy interrupt status bit, UPDATEI reports and acknowledges a change of
state from 1 to 0 in the UPDATEV bit of the Configuration register. This signifies that a page
copy is complete. This bit is cleared when read. When enabled by the UPDATEE bit, the INT
output reflects the state of this bit.
FRAMEI
The frame interrupt status bit reports the sampling of the CMP bit at the expected RC1FP
position. When enabled by FRAMEE, frequency of occurrence of FRAMEI is dependent on
MF_SWAP. When enabled by the FRAMEE bit, the INT output reflects the state of this bit.
MF_SWAP FRAMEI occurs every
00
01
10
11
1 frame
4 frame
4 frame
48 frame
This bit is cleared when read.
A change in the CMP input should be sequenced to occur as soon as possible after the
occurrence of FRAMEI. Changing CMP prior to the occurrence of FRAMEI may cause
unpredictable behavior as it may cause CMP to be sampled later than expected.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
96
PMC [ PMC-SIERRA, INC ]
