NSE-8G™ Standard Product Data Sheet
Preliminary
Register 048H: DCB C1 delay (RC1DLY) register.
Bit
Bit 31-6
Type
R
Function
Unused
Default
X
Bit 13-0
R/W
RC1DLY[13:0]
0
RC1DLY
This value, equaling the delay (in 77.76 MHz clock periods), between RC1FP and the arrival
of the C1 characters in the R8TD. This delay will synchronize the C1 input to the R8TD
blocks assuming all the C1 characters have arrived. As the delay on those links is dependent
on the system design, backplane propagation delays, cable lengths etc. This value will have to
be arrived at empirically. And will have an upper an lower limit for which the middle value
should be selected. The Operations section for more detail and some recommended starting
values.
MF_SWAP Legal Range (clock cycles)
00
01
10
11
26 – 9716
26 – 16383
26 – 16383
26 – 16383
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
91
PMC [ PMC-SIERRA, INC ]
