NSE-8G™ Standard Product Data Sheet
Preliminary
List of Figures
Figure 1 An OC-48 T1/E1 ADM (Individually Drop/Add any T1/E1 in STS-48) ..............14
Figure 2 An OC-48 T1/E1 ADM (Drop/Add up to STS-48 at STS-1 Granularity)............14
Figure 3 Any-Service-Any-Port TDM Access Solution....................................................15
Figure 4 Any-Service-Any-Port DS0-Granularity PHY Card ...........................................16
Figure 5 NSE- 8G Block Diagram Showing Functional Blocks.......................................17
Figure 6 NSE-8G UBGA-480 Ball Diagram (Bottom-View).............................................20
Figure 7 Analog Power Filter Circuit................................................................................39
Figure 8 Generic LVDS Link Block Diagram...................................................................40
Figure 9 Character Alignment State Machine .................................................................47
Figure 10 Frame Alignment State Machine.....................................................................48
Figure 11 In-Band Signaling Channel Message Format.................................................52
Figure 12 In-Band Signaling Channel Header Format....................................................52
Figure 13 Input Observation Cell (IN_CELL) ................................................................131
Figure 14 Output Cell (OUT_CELL) ..............................................................................132
Figure 15 Bidirectional Cell (IO_CELL) .........................................................................132
Figure 16 Layout of Output Enable and Bidirectional Cells...........................................133
Figure 17 Shutting Down a Link ....................................................................................135
Figure 18 “C1” Synchronization Control........................................................................137
Figure 19 TEMUX-84™/SBS/NSE/SBS/AAL1gator-32™ system DS0 Switching
with CAS .......................................................................................................138
Figure 20 CAS Multiframe Timing .................................................................................139
Figure 21 Switch Timing DSOs with CAS .....................................................................139
Figure 22 TEMUX-84/SBS/NSE/SBS/FREEDM-336 System DS0 Switch no
CAS...............................................................................................................140
Figure 23 Switch Timing - DSOs without CAS..............................................................141
Figure 24 Non DS0 Switch Timing ................................................................................142
Figure 25 Architecture of the RAM Input Interface........................................................144
Figure 26 C1 Position in the First Row..........................................................................149
Figure 27 Transport Overhead Affected by ILC ............................................................155
Figure 28 Example Graph .............................................................................................158
Figure 29 Time:Space:Time Switching in one NSE-8G and four Single-Ported
SBSs .............................................................................................................158
Figure 30 Example Graph .............................................................................................160
Figure 31 Example Problem..........................................................................................161
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
8
PMC [ PMC-SIERRA, INC ]
