NSE-8G™ Standard Product Data Sheet
Preliminary
Register 020H, 024H: CSTR #1 – 2 Control*
Bit
Type
Function
Unused
Default
Bit 31-16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
X
0
0
0
0
0
1
0
0
0
0
0
0
1
X
X
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved[11]
Reserved[10]
Reserved[9]
Reserved[8]
Reserved[7]
Reserved[6]
Reserved[5]
Reserved[4]
Reserved[3]
Reserved[2]
Reserved[1]
CSU_ENB
CSU_RSTB
Unused
Bit 4
Bit 3
Bit 2
Bit 1
Unused
Reserved[0]
Bit 0
R/W
This register provides reset control and enable control for CSTR block #1
Reserved[11:0]
The Reserved bits must be set to the indicated default value for correct operation of the NSE.
CSU_RSTB
The CSU_RSTB signal is a software reset signal that forces the CSU into reset. The CSU is
reset when the CSU_RSTB is logic 0. The CSU is also reset by the NSE-8G master analog
reset signal. When the CSU is reset, the reset signal should be held for at least 100us.
CSU_ENB
The CSU enable control signal (CSU_ENB) bit forces the CSU into low power configuration.
The CSU is disabled when CSU_ENB is logic one. The CSU is enabled when CSU_ENB is
logic 0.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
82
PMC [ PMC-SIERRA, INC ]
