NSE-8G™ Standard Product Data Sheet
Preliminary
Table of Contents
1
2
3
4
5
6
7
8
Features.....................................................................................................................11
Applications ...............................................................................................................12
References ................................................................................................................13
Application Examples ................................................................................................14
Block Diagram ...........................................................................................................17
Description.................................................................................................................19
Pin Diagram...............................................................................................................20
Pin Description...........................................................................................................24
8.1 Pin Description Table ........................................................................................24
8.2 Analog Power Filtering Recommendations.......................................................38
Functional Description...............................................................................................40
9.1 LVDS Overview.................................................................................................40
9.1.1 LVDS Receiver (RXLV) ........................................................................41
9.1.2 LVDS Transmitter (TXLV).....................................................................41
9.1.3 LVDS Transmit Reference (TXREF) ....................................................41
9.1.4 Data Recovery Unit (DRU)...................................................................42
9.1.5 Parallel to Serial Converter (PISO) ......................................................42
9.1.6 Clock Synthesis Unit (CSU) .................................................................42
9.2 Receive 8B/10B Frame Aligner (R8TD)............................................................42
9.2.1 FIFO Buffer...........................................................................................42
9.3 Transmit 8B/10B Encoder (T8TE).....................................................................43
9.3.1 SBI336S 8B/10B Character Encoding .................................................43
9.3.2 Serial TelecomBus 8B/10B Character Encoding..................................44
9.3.3 Serial SBI336S and TelecomBus Alignment ........................................46
9.3.4 Character Alignment Block...................................................................46
9.3.5 Frame Alignment ..................................................................................47
9.3.6 SBI336S Multiframe Alignment ............................................................49
9.4 DS0 Cross Bar switch (DCB)............................................................................49
9.5 Clock Synthesis and Transmit Reference Digital Wrapper (CSTR)..................50
9.6 Fabric Latency...................................................................................................50
9.7 JTAG Support....................................................................................................50
9.8 Microprocessor Interface ..................................................................................50
9.9 In-band Link Controller (ILC).............................................................................51
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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
3
PMC [ PMC-SIERRA, INC ]
