NSE-8G™ Standard Product Data Sheet
Preliminary
Table 18 Microprocessor Interface Write Access
Symbol
Parameter
Address to Valid Write Set-up Time
Min
10
Max
Units
ns
tS
tS
tS
AW
Data to Valid Write Set-up Time
Address to Latch Set-up Time
Address to Latch Hold Time
Valid Latch Pulse Width
20
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
DW
ALW
tH
ALW
L
tV
tS
Latch to Write Set-up
0
LW
tH
tH
tH
Latch to Write Hold
5
LW
DW
AW
WR
Data to Valid Write Hold Time
Address to Valid Write Hold Time
Valid Write Pulse Width
5
5
tV
40
Figure 40 Microprocessor Interface Write Timing
tSaw
tHaw
A[11:0]
tSalw
tVl
tHalw
tVwr
ALE
tSlw
CSB+WRB)
tSdw
tHdw
D[31:0]
VALID
Notes on Microprocessor Interface Write Timing:
1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals.
2. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tS
,
ALW
tH
ALW
, tV , tS
, and tH
are not applicable.
is not applicable if address latching is used.
L
LW
LW
3. Parameter tH
AW
4. When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 V point of the input to the 1.4 V point of the clock.
5. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds
from the 1.4 V point of the input to the 1.4 V point of the clock.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
175
PMC [ PMC-SIERRA, INC ]
