NSE-8G™ Standard Product Data Sheet
Preliminary
2. Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface
data bus, (D[15:0]).
3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
4. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tS
,
ALR
tH
, tV , tS , and tH
are not applicable.
ALR
L
LR LR
5. Parameter tH
AR
is not applicable if address latching is used.
6. When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 V point of the input to the 1.4 V point of the clock.
7. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds
from the 1.4 V point of the input to the 1.4 V point of the clock.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
174
PMC [ PMC-SIERRA, INC ]
