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PM8621 参数 Datasheet PDF下载

PM8621图片预览
型号: PM8621
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内容描述: NSE- 8G⑩标准产品数据表初步 [NSE-8G⑩ Standard Product Data Sheet Preliminary]
分类和应用:
文件页数/大小: 184 页 / 957 K
品牌: PMC [ PMC-SIERRA, INC ]
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NSE-8G™ Standard Product Data Sheet  
Preliminary  
The general multicast problem is not considered in this document. See the PMC NSE-8G  
documentation for descriptions of the use of multicast in a protection switching schemes; the  
same concepts apply to NSE/SBS fabrics.  
12.14 JTAG Support  
The NSE-8G supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1  
standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS,  
TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB  
input is the active-low reset signal used to reset the TAP controller. TCK is the test clock used to  
sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the  
TAP controller through its states. The basic boundary scan architecture is shown below.  
Figure 34 Boundary Scan Architecture  
Boundary Scan  
TDI  
Register  
Device Identification  
Register  
Bypass  
Register  
Instruction  
Mux  
Register  
DFF  
TDO  
and  
Decode  
Control  
TMS  
Test  
Access  
Port  
Select  
Tri-state Enable  
Controller  
TRSTB  
TCK  
The boundary scan architecture consists of a TAP controller, an instruction-register with  
instruction-decode, a bypass register, a device identification register and a boundary scan register.  
The TAP controller interprets the TMS input and generates control signals to load the instruction  
and data registers. The instruction register with instruction decode block is used to select the test  
to be executed and/or the register to be accessed. The bypass register offers a single-bit delay  
from primary input, TDI to primary output, TDO. The device identification register contains the  
device identification code.  
The boundary scan register allows testing of board inter-connectivity. The boundary scan register  
consists of a shift register place in series with device inputs and outputs. Using the boundary scan  
register, all digital inputs can be sampled and shifted out on primary output, TDO. In addition,  
patterns can be shifted in on primary input, TDI and forced onto all digital outputs.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use  
Document ID: PMC-2010850, Issue 1  
163  
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