PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Register 0x3A4 : THDL Indirect Block Data
Bit
Type
Function
Default
Bit 15
R/W
Reserved
Unused
0
XH
Bit 14
to
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
BPTR[10]
BPTR[9]
BPTR[8]
BPTR[7]
BPTR[6]
BPTR[5]
BPTR[4]
BPTR[3]
BPTR[2]
BPTR[1]
BPTR[0]
X
0
0
0
0
0
0
0
0
0
0
0
This register contains data read from the transmit block pointer RAM after an
indirect block read operation or data to be inserted into the transmit block pointer
RAM in an indirect block write operation.
BPTR[10:0]:
The indirect block pointer (BPTR[10:0]) configures the block pointer of the
block specified by the Indirect Block Select register. The block pointer to be
written to the transmit block pointer RAM, in an indirect write operation, must
be set up in this register before triggering the write. The block pointer value is
the block number of the next block in the linked list. A circular list of blocks
must be formed in order to use the block list as a channel FIFO buffer.
FPTR[10:0] reflects the value written until the completion of a subsequent
indirect block read operation.
When provisioning a channel FIFO, all blocks pointers must be re-written to
properly initialize the FIFO.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
137
PMC [ PMC-SIERRA, INC ]
