PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
DFCS:
The diagnose frame check sequence bit (DFCS) controls the inversion of the
FCS field inserted into the transmit packet. The value of DFCS to be written
to the channel provision RAM, in an indirect channel write operation, must be
set up in this register before triggering the write. When DFCS is set to one,
the FCS field in the outgoing HDLC stream is logically inverted allowing
diagnosis of downstream FCS verification logic. The outgoing FCS field is
not inverted when DFCS is set to zero. DFCS reflects the value written until
the completion of a subsequent indirect channel read operation.
INVERT:
The HDLC data inversion bit (INVERT) configures the HDLC processor to
logically invert the outgoing HDLC stream. The value of INVERT to be written
to the channel provision RAM, in an indirect channel write operation, must be
set up in this register before triggering the write. When INVERT is set to one,
the outgoing HDLC stream is logically inverted. The outgoing HDLC stream is
not inverted when INVERT is set to zero. INVERT reflects the value written
until the completion of a subsequent indirect channel read operation.
7BIT:
The least significant stuff enable bit (7BIT) configures the HDLC processor to
stuff the least significant bit of each octet in the outgoing channel stream. The
value of 7BIT to be written to the channel provision RAM, in an indirect
channel write operation, must be set up in this register before triggering the
write. When 7BIT is set high, the least significant bit (last bit of each octet
transmitted) does not contain channel data and is forced to the value
configured by the BIT8 register bit. When 7BIT is set low, the entire octet
contains valid data and BIT8 is ignored. 7BIT reflects the value written until
the completion of a subsequent indirect channel read operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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