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PM7385 参数 Datasheet PDF下载

PM7385图片预览
型号: PM7385
PDF下载: 下载PDF文件 查看货源
内容描述: 84 LINK , 672通道帧引擎和数据链路管理与ANY -PHY分组接口 [84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER WITH ANY-PHY PACKET INTERFACE]
分类和应用:
文件页数/大小: 244 页 / 2231 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7385 FREEDM-84A672  
DATA SHEET  
PMC-1990114  
ISSUE 6  
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER  
WITH ANY-PHY PACKET INTERFACE  
Reserved:  
The reserved bit must be set low for correct operation of the FREEDM-  
84A672 device.  
DELIN:  
The indirect delineate enable bit (DELIN) configures the HDLC processor to  
perform flag sequence insertion and bit stuffing on the outgoing data stream.  
The delineate enable bit to be written to the channel provision RAM, in an  
indirect channel write operation, must be set up in this register before  
triggering the write. When DELIN is set high, flag sequence insertion, bit  
stuffing and ,optionally, CRC generation is performed on the outgoing HDLC  
data stream. When DELIN is set low, the HDLC processor does not perform  
any processing (flag sequence insertion, bit stuffing nor CRC generation) on  
the outgoing stream. DELIN reflects the value written until the completion of  
a subsequent indirect channel read operation.  
CRC[1:0]:  
The CRC algorithm (CRC[1:0]) configures the HDLC processor to perform  
CRC generation on the outgoing HDLC data stream. The value of CRC[1:0]  
to be written to the channel provision RAM, in an indirect channel write  
operation, must be set up in this register before triggering the write. CRC[1:0]  
is ignored when DELIN is low. CRC[1:0] reflects the value written until the  
completion of a subsequent indirect channel read operation.  
Table 20 – CRC[1:0] Settings  
CRC[1]  
CRC[0]  
Operation  
0
0
1
1
0
1
0
1
No CRC  
CRC-CCITT  
CRC-32  
Reserved  
PROV:  
The indirect provision enable bit (PROV) reports the channel provision enable  
flag read from the channel provision RAM after an indirect channel read  
operation has completed. The provision enable flag to be written to the  
channel provision RAM, in an indirect write operation, must be set up in this  
register before triggering the write. When PROV is set high, the HDLC  
processor will service requests for data from the TCAS672 block. When  
PROV is set low, the HDLC processor will ignore requests from the TCAS672  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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