PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
XFER[3:0] + 1 blocks = 16 * (XFER[3:0] + 1) bytes
XFER[3:0] should be set such that the number of blocks transferred is at least
two fewer than the total allocated to the associated channel. XFER[3:0]
reflects the value written until the completion of a subsequent indirect channel
read operation.
OFFSET[1:0]:
The packet byte offset (OFFSET[1:0]) configures the partial packet processor
to insert invalid bytes at the beginning of a packet stored in the channel FIFO.
The value of OFFSET[1:0] to be written to the channel provision RAM, in an
indirect channel write operation, must be set up in this register before
triggering the write. The number of bytes inserted before the beginning of a
HDLC packet is defined by the binary value of OFFSET[1:0]. OFFSET[1:0]
reflects the value written until the completion of a subsequent indirect channel
read operation.
CRC[1:0]:
The CRC algorithm bits (CRC[1:0]) configures the HDLC processor to perform
CRC verification on the incoming data stream. The value of CRC[1:0] to be
written to the channel provision RAM, in an indirect channel write operation,
must be set up in this register before triggering the write. CRC[1:0] is ignored
when DELIN is low. CRC[1:0] reflects the value written until the completion of
a subsequent indirect channel read operation.
Table 19 – CRC[1:0] Settings
CRC[1]
CRC[0]
Operation
0
0
1
1
0
1
0
1
No Verification
CRC-CCITT
CRC-32
Reserved
INVERT:
The HDLC data inversion bit (INVERT) configures the HDLC processor to
logically invert the incoming HDLC stream from the RCAS672 before
processing it. The value of INVERT to be written to the channel provision
RAM, in an indirect channel write operation, must be set up in this register
before triggering the write. When INVERT is set to one, the HDLC stream is
logically inverted before processing. When INVERT is set to zero, the HDLC
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