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PM7385 参数 Datasheet PDF下载

PM7385图片预览
型号: PM7385
PDF下载: 下载PDF文件 查看货源
内容描述: 84 LINK , 672通道帧引擎和数据链路管理与ANY -PHY分组接口 [84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER WITH ANY-PHY PACKET INTERFACE]
分类和应用:
文件页数/大小: 244 页 / 2231 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7385 FREEDM-84A672  
DATA SHEET  
PMC-1990114  
ISSUE 6  
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER  
WITH ANY-PHY PACKET INTERFACE  
Reserved:  
The reserved bit must be set low for correct operation of the FREEDM-  
84A672 device.  
TAVAIL:  
The indirect transaction available bit (TAVAIL) reports the fill level of the partial  
packet buffer used in the logical FIFO of the current channel. TAVAIL is set  
high when the FIFO of the current channel contains sufficient data, as  
controlled by XFER[3:0], to result in a transfer across the receive APPI.  
TAVAIL is set low when the amount of receive data is too small to result in a  
transfer across the receive APPI. TAVAIL is updated by an indirect channel  
read operation.  
DELIN:  
The indirect delineate enable bit (DELIN) configures the HDLC processor to  
perform flag sequence delineation and bit de-stuffing on the incoming data  
stream. The delineate enable bit to be written to the channel provision RAM,  
in an indirect channel write operation, must be set up in this register before  
triggering the write. When DELIN is set high, flag sequence delineation and  
bit de-stuffing is performed on the incoming data stream. When DELIN is set  
low, the HDLC processor does not perform any processing (flag sequence  
delineation, bit de-stuffing nor CRC verification) on the incoming stream.  
DELIN reflects the value written until the completion of a subsequent indirect  
channel read operation.  
STRIP:  
The indirect frame check sequence discard bit (STRIP) configures the HDLC  
processor to remove the CRC from the incoming frame when writing the data  
to the channel FIFO. The FCS discard bit to be written to the channel  
provision RAM, in an indirect channel write operation, must be set up in this  
register before triggering the write. When STRIP is set high and CRC[1:0] is  
not equal to “00”, the received CRC value is not written to the FIFO. When  
STRIP is set low, the received CRC value is written to the FIFO. The bytes in  
buffer field of the RPD correctly reflect the presence/absence of CRC bytes in  
the buffer. The value of STRIP is ignored when DELIN is low. STRIP reflects  
the value written until the completion of a subsequent indirect channel read  
operation.  
PROV:  
The indirect provision enable bit (PROV) reports the channel provision enable  
flag read from the channel provision RAM after an indirect channel read  
operation has completed. The provision enable flag to be written to the  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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