PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x000 : FREEDM-84P672 Master Reset
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXH
Bit 16
Bit 15
R/W
Reset
0
Bit 14
Unused
XXXXH
to
Bit 0
This register provides software reset capability.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
RESET:
The RESET bit allows the FREEDM-84P672 to be reset under software
control. If the RESET bit is a logic one, the entire FREEDM-84P672 except
the PCI Interface is held in reset. This bit is not self-clearing. Therefore, a
logic zero must be written to bring the FREEDM-84P672 out of reset. Holding
the FREEDM-84P672 in a reset state places it into a low power, stand-by
mode. A hardware reset clears the RESET bit, thus negating the software
reset.
Note
Unlike the hardware reset input (RSTB), RESET does not force the FREEDM-
84P672's PCI pins tristate. RESET causes all registers to be set to their default
values.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
88
PMC [ PMC-SIERRA, INC ]
