PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x04 : Command/Status
Bit
Type
Function
Default
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R
PERR
SERR
MABT
RTABT
TABT
DVSLT[1]
DVSLT[0]
DPR
0
0
0
0
0
0
1
0
1
FBTBE
R
R
R
Reserved
66MHZ_CAPABLE
Reserved
0
1
00H
Bit 20
to
Bit 16
Bit 15
R
Reserved
00H
to
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R/W
R
R/W
R
R
R
R/W
R/W
R
FBTBEN
SERREN
ADSTP
PERREN
VGASNP
MWAI
0
0
0
0
0
0
0
0
0
0
SPCEN
MSTREN
MCNTRL
IOCNTRL
The lower 16 bits of this register make up the Command register which provides
basic control over the GPIC's ability to respond to PCI accesses. When a 0 is
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
286
PMC [ PMC-SIERRA, INC ]
