PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
UF[15:0]:
The UF[15:0] bits reports the number of transmit FIFO underflow events that
have been detected since the last time this register was polled. This register
is polled by writing to the FREEDM-84P672 Master Clock / Frame Pulse
Activity Monitor and Accumulation Trigger register. The write access transfers
the internally accumulated error count to the FIFO underflow register and
simultaneously resets the internal counter to begin a new cycle of error
accumulation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
265
PMC [ PMC-SIERRA, INC ]
