PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
TDQ_RDYN[2:0]:
The TDQ_RDYN[2:0] field sets the number of transmit descriptor references
(TDRs) that must be read from the TDR Ready Queue before the TDR Ready
interrupt (TDQRDYI) is asserted, as follows:
Table 30 – TDQ_RDYN[2:0] Settings
TDQ_RDYN[2:0]
No of TDRs
000
001
010
011
100
101
110
111
1
4
6
8
16
32
Reserved
Reserved
TDQ_FRN[1:0]:
The TDQ_FRN[1:0] field sets the number of times that a block of TDRs are
written to the TDR Free Queue from the TMAC672s internal cache before the
TDR Free Queue Interrupt (TDQFI) is asserted, as follows:
Table 31 – TDQ_FRN[1:0] Settings
TDQ_FRN[1:0]
No of Reads
00
01
10
11
1
4
8
Reserved
FQFLUSH:
The Free Queue Flush bit (FQFLUSH) may be used to initiate a dump of the
free queue cache retained locally within the TMAC672 to the free queue
located in PCI host memory. When the FQFLUSH bit is set high, the
TMAC672 dumps the contents of the free queue cache to the free queue in
PCI host memory. The FQFLUSH bit is self clearing and will reset to zero
when the flush is complete. Setting the FQFLUSH bit to zero has no affect.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
196
PMC [ PMC-SIERRA, INC ]
