PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x02C : FREEDM-84P672 Master SBI Interrupt Status
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXXXXXH
Bit 1
Bit 0
R
SBIEXTI
X
This register reports the interrupt status for various events detected or initiated
by the SBI circuitry within the FREEDM-84P672. Reading this register
acknowledges and clears the interrupts.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
SBIEXTI:
The SBI Extracter interrupt status bit (SBIEXTI) reports an error condition
from the SBI Extract block to the PCI host. SBIEXTI remains valid when
interrupts are disabled and may be polled to detect SBI Extract block error
conditions.
Note
The only error condition which the SBI Extract block reports is a parity error
on the SBI DROP BUS. If parity errors occur, the SBI EXTRACT Parity Error
Interrupt Reason register (0x5DC) may be read to obtain more detailed
information concerning the error.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
106
PMC [ PMC-SIERRA, INC ]
