RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
1. Each of RD[31:28] has been sampled low and sampled high by rising
edges of the corresponding RCLK[31:28] inputs, or
2. Each of RD[31:28] has been sampled low and sampled high by rising
edges of the RMVCK[3] input, or
3. RD[28] has been sampled low and sampled high by rising edges of the
RMV8DC input.
RLGA[7] is set low when this register is read.
TLGA[0]:
The transmit link group #0 active bit (TLGA[0]) monitors for low to high
transitions on the TCLK[3:0] & TMVCK[0] inputs. TLGA[0] is set high when
either:
1. Rising edges have been observed on all four TCLK[3:0] inputs, or
2. A rising edge has been observed on the TMVCK[0] input.
TLGA[0] is set low when this register is read.
TLGA[1]:
The transmit link group #1 active bit (TLGA[1]) monitors for low to high
transitions on the TCLK[7:4] & TMVCK[1] inputs. TLGA[1] is set high when
either:
1. Rising edges have been observed on all four TCLK[7:4] inputs, or
2. A rising edge has been observed on the TMVCK[1] input.
TLGA[1] is set low when this register is read.
TLGA[2]:
The transmit link group #2 active bit (TLGA[2]) monitors for low to high
transitions on the TCLK[11:8] & TMVCK[2] inputs. TLGA[2] is set high when
either:
1. Rising edges have been observed on all four TCLK[11:8] inputs, or
2. A rising edge has been observed on the TMVCK[2] input.
TLGA[2] is set low when this register is read.
TLGA[3]:
The transmit link group #3 active bit (TLGA[3]) monitors for low to high
transitions on the TCLK[15:12] & TMVCK[3] inputs. TLGA[3] is set high when
either:
1. Rising edges have been observed on all four TCLK[15:12] inputs, or
2. A rising edge has been observed on the TMVCK[3] input.
TLGA[3] is set low when this register is read.
PROPRIETARY AND CONFIDENTIAL
83
PMC [ PMC-SIERRA, INC ]
