RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
RLGA[4]:
The receive link group #4 active bit (RLGA[4]) monitors for transitions on the
RD[19:16] and RCLK[19:16]/RMVCK[2]/RMV8DC inputs. RLGA[4] is set high
when either:
1. Each of RD[19:16] has been sampled low and sampled high by rising
edges of the corresponding RCLK[19:16] inputs, or
2. Each of RD[19:16] has been sampled low and sampled high by rising
edges of the RMVCK[2] input, or
3. RD[16] has been sampled low and sampled high by rising edges of the
RMV8DC input.
RLGA[4] is set low when this register is read.
RLGA[5]:
The receive link group #5 active bit (RLGA[5]) monitors for transitions on the
RD[23:20] and RCLK[23:20]/RMVCK[2]/RMV8DC inputs. RLGA[5] is set high
when either:
1. Each of RD[23:20] has been sampled low and sampled high by rising
edges of the corresponding RCLK[23:20] inputs, or
2. Each of RD[23:20] has been sampled low and sampled high by rising
edges of the RMVCK[2] input, or
3. RD[20] has been sampled low and sampled high by rising edges of the
RMV8DC input.
RLGA[5] is set low when this register is read.
RLGA[6]:
The receive link group #6 active bit (RLGA[6]) monitors for transitions on the
RD[27:24] and RCLK[27:24]/RMVCK[3]/RMV8DC inputs. RLGA[6] is set high
when either:
1. Each of RD[27:24] has been sampled low and sampled high by rising
edges of the corresponding RCLK[27:24] inputs, or
2. Each of RD[27:24] has been sampled low and sampled high by rising
edges of the RMVCK[3] input, or
3. RD[24] has been sampled low and sampled high by rising edges of the
RMV8DC input.
RLGA[6] is set low when this register is read.
RLGA[7]:
The receive link group #7 active bit (RLGA[7]) monitors for transitions on the
RD[31:28] and RCLK[31:28]/RMVCK[3]/RMV8DC inputs. RLGA[7] is set high
when either:
PROPRIETARY AND CONFIDENTIAL
82
PMC [ PMC-SIERRA, INC ]
