RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
2. Microprocessor Interface timing applies to normal mode register accesses only.
3. In non-multiplexed address/data bus applications, ALE should be held high,
parameters tS
, tH , tV , tS , and tH are not applicable.
ALR ALR L LR LR
4. Parameter tH is not applicable if address latching is used.
AR
Table 27 – Microprocessor Interface Write Access (Figure 42)
Symbol
Description
Min
10
20
10
10
5
Max
Units
ns
tS
tS
tS
Address to Valid Write Set-up Time
Data to Valid Write Set-up Time
Address to Latch Set-up Time
Address to Latch Hold Time
Valid Latch Pulse Width
Latch to Write Set-up
AW
ns
DW
ALW
ns
tH
ns
ALW
tV
tS
ns
L
0
ns
LW
tH
tH
tH
Latch to Write Hold
5
ns
LW
DW
AW
WR
Data to Valid Write Hold Time
Address to Valid Write Hold Time
Valid Write Pulse Width
5
ns
5
ns
tV
20
ns
PROPRIETARY AND CONFIDENTIAL
217
PMC [ PMC-SIERRA, INC ]
