RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Figure 40 – Transmit Any-PHY Packet Interface Timing
TXCLK
tS
tH
TXADDR[12:0]
TXDATA[15:0]
TXPRTY, TSX
TEOP, TMOD
TERR
APPI
APPI
tP
tZ
APPI
APPI
TPAn[2:0]
TRDY
TPAn[2:0]
TRDY
tZD
APPI
TPAn[2:0]
TRDY
Table 26 – Microprocessor Interface Read Access (Figure 41)
Symbol
tS
Description
Min
10
5
Max
Units
ns
Address to Valid Read Set-up Time
Address to Valid Read Hold Time
Address to Latch Set-up Time
Address to Latch Hold Time
Valid Latch Pulse Width
Latch to Read Set-up
AR
tH
ns
AR
tS
10
10
5
ns
ALR
tH
ns
ALR
L
tV
tS
ns
0
ns
LR
tH
Latch to Read Hold
5
ns
LR
PROPRIETARY AND CONFIDENTIAL
215
PMC [ PMC-SIERRA, INC ]
