RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
11
OPERATIONS
This section presents connection details to the PM4388 TOCTL device, and
operating details for the JTAG boundary scan feature.
11.1 TOCTL Connections
The required connections between the PM4388 TOCTL and the FREEDM-
32A256 are shown in the following table:
Table 20 – FREEDM–TOCTL Connections
FREEDM Pin
Direction
TOCTL Pin
RCLK[n]
RD[n]
n.c.
TCLK[n]
TD[n]
H
H
H
H
J
ICLK/ISIG[m]
ID[m]
IFP[m]
EFP/RCLK/ESIG[m]
ED[m]
All 8 framers in the TOCTL should be programmed to operate in “Clock Master:
NxDS0” mode in both the ingress and egress direction.
11.2 JTAG Support
The FREEDM-32A256 supports the IEEE Boundary Scan Specification as
described in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of
the five standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP
controller and the boundary scan registers. The TRSTB input is the active low
reset signal used to reset the TAP controller. TCK is the test clock used to
sample data on input, TDI and to output data on output, TDO. The TMS input is
used to direct the TAP controller through its states. The basic boundary scan
architecture is shown below.
PROPRIETARY AND CONFIDENTIAL
180
PMC [ PMC-SIERRA, INC ]
