RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Figure 6 – Input Observation Cell (IN_CELL)
IDCODE
Scan Chain Out
INPUT
to internal
logic
Input
Pad
G1
G2
SHIFT-DR
1 2
1 2
1 2
1 2
D
MUX
C
I.D. Code bit
CLOCK-DR
Scan Chain In
In this diagram and those that follow, CLOCK-DR is equal to TCK when the
current controller state is SHIFT-DR or CAPTURE-DR, and unchanging
otherwise. The multiplexor in the center of the diagram selects one of four
inputs, depending on the status of select lines G1 and G2. The ID Code bit is as
listed in the table above.
PROPRIETARY AND CONFIDENTIAL
176
PMC [ PMC-SIERRA, INC ]
