RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x384 : THDL Indirect Channel Data #1
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R/W
R/W
R/W
R/W
W
W
W
W
W
W
W
W
W
W
W
W
PROV
CRC[1]
CRC[0]
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
DELIN
Reserved
FPTR[10]
FPTR[9]
FPTR[8]
FPTR[7]
FPTR[6]
FPTR[5]
FPTR[4]
FPTR[3]
FPTR[2]
FPTR[1]
FPTR[0]
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register contains data read from the channel provision RAM after an indirect
channel read operation or data to be inserted into the channel provision RAM in
an indirect channel write operation.
FPTR[10:0]:
The indirect FIFO block pointer (FPTR[10:0]) informs the partial packet buffer
processor about the circular linked list of blocks to use for a FIFO for the
channel. The FIFO pointer to be written to the channel provision RAM, in an
indirect write operation, must be set up in this register before triggering the
write. The FIFO pointer value can be any one of the block numbers
provisioned, by indirect block write operations, to form the circular buffer.
PROPRIETARY AND CONFIDENTIAL
119
PMC [ PMC-SIERRA, INC ]
