RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x220 : RHDL Configuration
Bit
Type
Function
Default
Bit 15
to
Unused
XXH
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
LENCHK
TSTD
0
0
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
X
X
X
X
X
X
X
X
This register configures all provisioned receive channels.
TSTD:
The telecom standard bit (TSTD) controls the bit ordering of the HDLC data
transferred across the receive APPI. When TSTD is set low, the least
significant bit of each byte on the receive APPI bus (AD[0] and AD[8]) is the
first HDLC bit received and the most significant bit of each byte (AD[7] and
AD[15]) is the last HDLC bit received (datacom standard). When TSTD is set
high, AD[0] and AD[8] are the last HDLC bits received and AD[7] and AD[15]
are the first HDLC bits received (telecom standard).
LENCHK:
The packet length error check bit (LENCHK) controls the checking of receive
packets that are longer than the maximum programmed length. When
LENCHK is set high, receive packets are aborted and the remainder of the
frame discarded when the packet exceeds the maximum packet length given
by MAX[15:0]. When LENCHK is set low, receive packets are not checked for
maximum size and MAX[15:0] must be set to ‘hFFFF.
PROPRIETARY AND CONFIDENTIAL
115
PMC [ PMC-SIERRA, INC ]
