RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x3B0 : THDL Configuration
Bit
Type
Function
Default
Bit 15
to
Unused
XXH
Bit 10
Bit 9
Bit 8
Bit 7
R/W
R/W
R/W
BIT8
TSTD
Reserved
Unused
0
0
0
Bit 6
to
XH
Bit 4
Bit 3
to
R/W
Reserved
0H
Bit 0
This register configures all provisioned channels.
Reserved:
The reserved bits must be set low for correct operation of the FREEDM-
32A256 device.
TSTD:
The telecom standard bit (TSTD) controls the bit ordering of the HDLC data
transferred on the transmit APPI. When TSTD is set low, the least significant
bit of the each byte on the transmit APPI bus (AD[0] and AD[8]) is the first
HDLC bit transmitted and the most significant bit of each byte (AD[7] and
AD[15]) is the last HDLC bit transmitted (datacom standard). When TSTD is
set high, AD[0] and AD[8] are the last HDLC bit transmitted and AD[7] and
AD[15] are the first HDLC bit transmitted (telecom standard).
BIT8:
The least significant stuff control bit (BIT8) carries the value placed in the
least significant bit of each octet when the HDLC processor is configured
(7BIT set high) to stuff the least significant bit of each octet in the
corresponding transmit link (TD[n]). When BIT8 is set high, the least
significant bit (last bit of each octet transmitted) is forced high. When BIT8 is
PROPRIETARY AND CONFIDENTIAL
133
PMC [ PMC-SIERRA, INC ]
