RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
9.5.2
9.5.3
9.5.4
9.5.5
DMA TRANSACTION CONTROLLER...........................56
WRITE DATA PIPELINE/MUX.......................................56
DESCRIPTOR INFORMATION CACHE........................56
FREE QUEUE CACHE..................................................57
9.6
9.7
PCI CONTROLLER......................................................................57
9.6.1
9.6.2
9.6.3
9.6.4
9.6.5
MASTER MACHINE ......................................................58
MASTER LOCAL BUS INTERFACE..............................60
TARGET MACHINE.......................................................61
CBI BUS INTERFACE ...................................................63
ERROR / BUS CONTROL.............................................63
TRANSMIT DMA CONTROLLER.................................................63
9.7.1
9.7.2
9.7.3
9.7.4
9.7.5
9.7.6
DATA STRUCTURES ....................................................64
TASK PRIORITIES ........................................................76
DMA TRANSACTION CONTROLLER...........................76
READ DATA PIPELINE..................................................76
DESCRIPTOR INFORMATION CACHE........................76
FREE QUEUE CACHE..................................................77
9.8
9.9
TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER77
9.8.1
9.8.2
TRANSMIT HDLC PROCESSOR..................................77
TRANSMIT PARTIAL PACKET BUFFER PROCESSOR78
TRANSMIT CHANNEL ASSIGNER .............................................80
9.9.1
9.9.2
9.9.3
LINE INTERFACE TRANSLATOR (LIT) ........................82
LINE INTERFACE..........................................................82
PRIORITY ENCODER...................................................83
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
iii
PMC [ PMC-SIERRA, INC ]
