RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Symbol
Description
Min
Max
Units
TMV8FPC Duty Cycle
TMV8DC to TMV8FPC skew
TFPB[3:0] Set-Up Time
TFPB[3:0] Hold Time
40
-10
50
50
50
50
3
60
10
%
tP
tS
ns
ns
ns
ns
ns
ns
MVC
TFPB
tH
TFPB
TS
TH
TFP8B Set-Up Time
TFP8B
TF8PB
TFP8B Hold Time
t
t
t
TCLK[2:0] Low to TD[2:0] Valid
12
25
25
P
P
P
TD
TCLK[31:3] Low to TD[31:3] Valid
4
4
ns
ns
TD
TMVCK[3:0] Low to TD[31:0] Valid
(2.048 Mbps H-MVIP Mode)
TD_2MVIP
t
t
TMV8DC Low to TD[31:0] Valid
4
25
5
ns
ns
P
P
TD_8MVIP
RBD
(8.192 Mbps H-MVIP Mode)
RBCLK Low to RBD Valid
-5
Notes on Output Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of
the reference signal to the 1.4 Volt point of the output.
2. Maximum and minimum output propagation delays are measured with a 50 pF load
on all the outputs, except for the TD[2:0] outputs, which are measured with a 20pF
load, and the PCI outputs/bidirs, which are measured with a 10pF load. Maximum
propagation delay for TD[2:0] increases by typically 1 ns for each 10 pF of extra
load.
3. Output propagation delays of signal outputs that are specified in relation to a
reference output are measured with a 50 pF load on both the signal output and the
reference output.
4. Applicable only to channelised T1/J1 links and measured between framing bits.
5. Applicable only to channelised E1 links and measured between framing bytes.
6. Applicable only to unchannelised links of any format and measured between any
two TCLK rising edges.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
312
PMC [ PMC-SIERRA, INC ]
