RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
written to all bits in the command register, the GPIC is logically disconnected
from the PCI bus for all accesses except configuration accesses. The upper 16-
bits is used to record status information for PCI bus related events. Reads to the
status portion of this register behave normally. Writes are slightly different in that
bits can be reset, but not set. A bit is reset whenever the register is written, and
the data in the corresponding bit location is a 1.
IOCNTRL:
When IOCNTRL is set to zero, the GPIC will not respond to PCI bus I/O
accesses.
MCNTRL:
When MCNTRL is set to one, the GPIC will respond to PCI bus memory
accesses. Clearing MCNTRL disables memory accesses.
MSTREN:
When MSTREN is set to one, the GPIC can act as a Master. Clearing
MSTREN disables the GPIC from becoming a Master.
SPCEN:
The GPIC does not decode PCI special cycles. The SPCEN bit is forced low.
MWAI:
The GPIC does not generate memory-write-and-invalidate commands. The
MWAI bit is forced low.
VGASNP:
The GPIC is not a VGA device. The VGASNP bit is forced low.
PERREN:
When the PERREN bit is set to one, the GPIC can report parity errors.
Clearing the PERREN bit causes the GPIC to ignore parity errors.
ADSTP:
The GPIC does not perform address and data stepping. The ADSTP bit is
forced low.
SERREN:
When the SERREN bit is set high, the GPIC can drive the SERRB line.
Clearing the SERREN bit disables the SERRB line. SERREN and PERREN
must be set to report an address parity error.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
255
PMC [ PMC-SIERRA, INC ]
