RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Register 0x500 : PMON Status
Bit
Type
Function
Default
Bit 31
Unused
XXXXXXXH
to
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
C2DET
C1DET
UFDET
OFDET
Unused
Unused
X
X
X
X
X
X
This register contains status information indicating whether a non-zero count has
been latched in the count registers.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
OFDET:
The overflow detect bit (OFDET) indicates the status of the PMON Receive
FIFO Overflow Count register. OFDET is set high when overflow events have
occurred during the latest PMON accumulation interval. OFDET is set low if
no overflow events are detected.
UFDET:
The underflow detect bit (UFDET) indicates the status of the PMON Transmit
FIFO Underflow Count register. UFDET is set high when underflow events
have occurred during the latest PMON accumulation interval. UFDET is set
low if no underflow events are detected.
C1DET:
The configurable event #1 detect bit (C1DET) indicates the status of the
PMON Configurable Count #1 register. C1DET is set high when selected
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
242
PMC [ PMC-SIERRA, INC ]
